Intel Proves 45-nm Process With Test Chips

Mark Hachman - ExtremeTech Wed Jan 25, 1:21 PM ET

Intel Corp. said this week that it had produced working silicon on its next-generation 45-nanometer manufacturing process, and is on schedule to move the technology into production in the second half of 2007.

Intel's announcement from its research division will help keep its production schedule moving forward into smaller and smaller geometries. Intel currently manufactures chips from two fabs using 65-nm equipment, and more than 50 percent of its PC microprocessors will be manufactured on the newer 65-nm chips beginning in the third quarter of the is year, Intel executives said in a teleconference.

The shift is the practical application of Moore's Law, Gordon Moore's theorem that transistor counts double every 12 to 18 months. Like any good equation, that axiom can be rewritten to mean that as transistor sizes shrink, the overall speed of the chip can be pushed faster and faster, or that the power consumed by the semiconductor will drop, all other things being equal.

Intel traditionally has prided itself on its manufacturing prowess, part of the leverage it exerts in its position atop the PC microprocessor sales chart.

According to Mark Bohr, an Intel senior fellow and director of its process-technology and integration schedules, the 45-nm "P1266" process can either mean twice the transistor density, or a 30 percent reduction in switching power compared to the 65-nm process. Designers also have a choice to either cut leakage power by 5X -- the charge that trickles or leaks away when a device is running in a low-power mode -- or trade that for a 20 percent improvement in transistor switching speed.

Specificaly, Intel showed a 153-Mbit, 119-sq. mm SRAM chip containing over a billion transistors, which had been fabricated using the 45-nm process. For Intel, the key is not to produce chips using embedded or discrete memory, but to manufacture logic components that form the foundation for its microprocessors. According to Bohr, the test chips contain some transistor and interconnect features used in the logic process.

Intel uses a "bulk" silicon process, a different process than rival Advanced Micro Devices, which uses a "depleted silicon on insulator" (SOI) manufacturing process to achieve faster speeds. In the past, Intel has been critical of SOI, and Intel engineers have claimed that SOI risks becoming structurally more fragile as the manufacturing processes use finer linewidths. Those same challenges will be faced by Intel, although Bohr declind to discuss the specific solutions Intel had found to solve these.

"Every new technology is getting more and more challenging to scale," Bohr said. "We have a pretty talented team of engineers. As we go to finer linewidths, though, we need to ask what sort of lithography tool and techniques are needed to extend the current 193-nm lithography -- it gets more challenging. Fortunately, we have found some tricks and techniques to do that."

Intel also plans a low-power derivative of the 65-nm manufacturing process for handheld chips and chipsets, Bohr added.